1. Field of the Invention
The present invention relates to an improvement on a scanning circuit used in a solid-state image pickup device etc.
2. Description of the Prior Art
Usually, a solid-stage image pickup device includes a scanning circuit comprising a multiplicity of photoelectric conversion elements such as PN junction photodiodes arranged in a linear or two-dimensional pattern, switching elements such as MOS field effect transistors (hereafter referred to as MOSFET) to take the outputs out of the photoelectric conversion elements onto an output line selectively, and a shift register to generate pulses to actuate the switching elements in time sequence. In a preferable case, the elements and the circuits constituting the solid-state image pickup device are formed in the surface of a single crystal silicon substrate through integrated circuit techniques. As an integrated circuit of the scanning circuit for the image pickup device is known a device in which a multiplicity of unit circuits, each consisting of four MOSFET's, are connected in cascade one after another so that by applying two clock signals having different phases to each unit circuit a train of pulses shifted by a delay time proper to the clock signals may be derived from the unit circuit sequentially. Such a means has several merits. Namely, it is small and light and its power consumption is small while its reliability is very high.
In the conventional scanning circuit, however, the conductance g.sub.m of the used MOSFET imposes a restriction upon the available frequencies of the clock signal: if the frequency or pulse repetition rate is too high, the circuit cannot operate properly so that the input pulses cannot be shifted. The conventional scanning circuit has, therefore, a drawback that the upper limit of the operating frequency is at most 4 to 5 MHz.
It is fundamentally possible to heighten the upper limit of the operating frequency by increasing the conductance g.sub.m of each MOSFET, but in such a case the area occupied by the MOSFET becomes larger so that the high density integration of the circuit is impossible.
Moreover, since clock pulses are used in this scanning circuit, noise produced as a result of the differentiation of the pulses through parasitic capacitances etc. is mixed to the output signal to degrade the S/N ratio.